1. Field of the Invention
This invention relates generally to voltage regulator circuits. More particularly, this invention relates to low dropout voltage regulator circuits. Even more particularly this invention relates to low dropout voltage regulator circuits having dynamic voltage control.
2. Description of Related Art
Battery powered applications such as smart-phones and tablet computers demand long battery life and therefore highly power efficient circuits. Often, the power supply voltage of digital circuits for the battery power applications must be adjusted during operation to minimize power consumption, since the power dissipated is proportional to the square of the power supply voltage. To achieve the required speed of operation, a certain minimum supply voltage is required. As demand fluctuates, so the supply voltage is adjusted as required.
The power supply for these types of circuits is often regulated down from the main battery by a voltage regulator, e.g. buck converter or linear regulator.
Buck regulators are generally power efficient but can consume a significant area and need bulky external components (inductors). These circuits are often used for higher load currents where the area of the control circuit is not significant compared with the size of the power switches.
However, for applications which require only a modest load current, the area penalty of a buck converter may be unacceptable. In such cases, the use of a low dropout voltage regulator (LDO) can be more area efficient although with some loss of energy efficiency.
A low dropout regulator is a class of linear regulator that is designed to minimize the saturation of the output pass transistor and its drive requirements. A low-dropout linear regulator will operate with input voltages only slightly higher than the desired output voltage. FIG. 1 is a schematic of a low dropout voltage regulator of the prior art. The main components of a low dropout voltage regulator are a power field effect transistor MOut having a source and bulk connected to a battery BAT to receive a battery voltage Vbat. The gate of the power field effect transistor MOut is connected to an output of a differential error amplifier Op1. One input of the differential error amplifier Op1 monitors the fraction of the output determined by the resistor ratio of R1 and R2. The second input to the differential error amplifier Op1 is from a stable voltage reference (bandgap reference) VRef. If the output voltage rises too high relative to the reference voltage VRef, the drive to the power field effect transistor Mout changes to maintain a constant output voltage VOut developed across the load capacitance CLoad.